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1 tm file number 4811.3 ITF87068SQT 9a, 20v, 0.015 ohm, p-channel, 2.5v speci?d power mosfet packaging symbol features ultra low on-resistance -r ds(on) = 0.015 ?, v gs = ? 4.5v -r ds(on) = 0.016 ?, v gs = ? 4.0v -r ds(on) = 0.023 ?, v gs = ? 2.5v 2.5v gate drive capability gate to source protection diode simulation models - temperature compensated pspice?and saber electrical models - spice and saber thermal impedance models - www.intersil.com peak current vs pulse width curve transient thermal impedance curve vs board mounting area switching time vs r gs curves absolute maximum ratings t a = 25 o c, unless otherwise specified tssop-8 4 1 2 3 5 source(2) drain(8) drain(1) source(7) source(6) drain(5) source(3) gate(4) ordering information part number package brand ITF87068SQT tssop-8 87068 note: when ordering, use the entire part number. ITF87068SQT2 is available only in tape and reel. ITF87068SQT units drain to source voltage (note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v dss -20 v drain to gate voltage (r gs = 20k ? ) (note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v dgr -20 v gate to source voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v gs 1 2v drain current continuous (t a = 25 o c, v gs = -4.5v) (note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . i d continuous (t a = 25 o c, v gs = -4.0v) (note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . i d continuous (t a = 100 o c, v gs = -4.0v) (note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . i d continuous (t a = 100 o c, v gs = -2.5v) (note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . i d pulsed drain current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .i dm 9.0 9.0 5.5 4.5 figure 4 a a a a power dissipation (note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . p d derate above 25 o c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.0 16 w mw/ o c operating and storage temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . t j , t stg -55 to 150 o c maximum temperature for soldering leads at 0.063in (1.6mm) from case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .t l package body for 10s, see techbrief tb370 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . t pkg 300 260 o c o c notes: 1. t j = 25 o c to 125 o c. 2. 62.5 o c/w measured using fr-4 board with 1.0 in 2 (645.2 mm 2 ) copper pad at 10s. caution: stresses above those listed in ?bsolute maximum ratings may cause permanent damage to the device. this is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this speci?ation is not implied. data sheet july 2000 caution: these devices are sensitive to electrostatic discharge. follow proper esd handling procedures. saber is a trademark of analogy inc. pspice?is a registered trademark of microsim corporation. 1-888-intersil or 321-724-7143 | intersil and design is a trademark of intersil corporation. | copyright intersil corporation 2000
2 electrical speci?ations t a = 25 o c, unless otherwise specified parameter symbol test conditions min typ max units off state specifications drain to source breakdown voltage bv dss i d = 250 a, v gs = 0v figure 11 -20 - - v zero gate voltage drain current i dss v ds = -20v, v gs = 0v - - -10 a gate to source leakage current i gss v gs = 12v - - 10 a on state specifications gate to source threshold voltage v gs(th) v gs = v ds , i d = 250 a figure 10 -0.5 - -1.5 v drain to source on resistance r ds(on) i d = 9.0a, v gs = -4.5v figures 8,9 - 0.012 0.015 ? i d = 5.5a, v gs = -4.0v figure 8 - 0.013 0.016 ? i d = 4.5a, v gs = -2.5v figure 8 - 0.017 0.023 ? thermal specifications thermal resistance junction to ambient r ja pad area = 1.0 in 2 (645.2 mm 2 ) (note 2) - - 62.5 o c/w pad area = 0.035 in 2 (22.4 mm 2 ) figure 20 - - 165.4 o c/w pad area = 0.0045 in 2 (2.88 mm 2 ) figure 20 - - 206.8 o c/w switching specifications v gs = -2.5v turn-on delay time t d(on) v dd = -10v, i d = 4.5a v gs = -2.5v, r gs = 5 ? figures 14, 18, 19 -25- ns rise time t r - 120 - ns turn-off delay time t d(off) -50- ns fall time t f -68- ns switching specifications v gs = -4.5v turn-on delay time t d(on) v dd = -10v, i d = 9.0a v gs = -4.5v, r gs = 5 ? figures 15, 18, 19 -17- ns rise time t r - 110 - ns turn-off delay time t d(off) -68- ns fall time t f -92- ns gate charge specifications total gate charge q g(tot) v gs = 0v to -4.5v v dd = -10v, i d = 9.0a, i g(ref) = -1.0ma figures 13, 16, 17 -28-nc gate charge at -2v q g(-2) v gs = 0v to -2v - 14 - nc threshold gate charge q g(th) v gs = 0v to -0.5v - 1.5 - nc gate to source gate charge q gs - 3.5 - nc gate to drain ?iller?charge q gd - 5.5 - nc capacitance specifications input capacitance c iss v ds = -10v, v gs = 0v, f = 1mhz figure 12 - 3000 - pf output capacitance c oss - 685 - pf reverse transfer capacitance c rss - 315 - pf source to drain diode speci?ations parameter symbol test conditions min typ max units source to drain diode voltage v sd i sd = -9.0a - -0.8 - v reverse recovery time t rr i sd = -9.0a, di sd /dt = 100a/ s - 26 - ns reverse recovered charge q rr i sd = -9.0a, di sd /dt = 100a/ s - 12 - nc ITF87068SQT
3 typical performance curves figure 1. normalized power dissipation vs ambient temperature figure 2. maximum continuous drain current vs ambient temperature figure 3. normalized maximum transient thermal impedance figure 4. peak current capability t a , ambient temperature ( o c) power dissipation multiplier 0 0 25 50 75 100 150 0.2 0.4 0.6 0.8 1.0 1.2 125 -6 -8 -10 50 75 100 125 150 0 25 i d , drain current (a) t a , ambient temperature ( o c) v gs = -2.5v, r ja = 206.8 o c/w v gs = -4.5v, r ja = 62.5 o c/w -2 -4 0.01 1 3 10 -4 10 -3 10 -2 10 -1 10 0 10 1 10 2 10 3 0.001 10 -5 t, rectangular pulse duration (s) z ja , normalized thermal impedance single pulse notes: duty factor: d = t 1 /t 2 peak t j = p dm x z ja x r ja + t a p dm t 1 t 2 duty cycle - descending order 0.5 0.2 0.1 0.05 0.01 0.02 r ja = 62.5 o c/w 0.1 10 100 1000 5 10 -4 10 -3 10 -2 10 -1 10 0 10 1 10 2 10 3 10 -5 i dm , peak current (a) t, pulse width (s) v gs = -4.5v r ja = 62.5 o c/w transconductance may limit current in this region t c = 25 o c i = i 25 150 - t a 125 for temperatures above 25 o c derate peak current as follows: v gs = -2.5v ITF87068SQT
4 figure 5. forward bias safe operating area figure 6. transfer characteristics figure 7. saturation characteristics figure 8. drain to source on resistance vs gate voltage and drain current figure 9. normalized drain to source on resistance vs junction temperature figure 10. normalized gate threshold voltage vs junction temperature typical performance curves (continued) -1 -10 -100 -1 -10 -50 -300 100 s 10ms 1ms v ds , drain to source voltage (v) i d , drain current (a) limited by r ds(on) area may be operation in this t j = max rated t a = 25 o c single pulse r ja = 62.5 o c/w -0 -5 -10 -15 -20 -25 -0.5 -1.0 -1.5 -2.0 i d, drain current (a) v gs , gate to source voltage (v) pulse duration = 80 s duty cycle = 0.5% max v dd = -15v t j = 25 o c t j = 150 o c t j = -55 o c i d , drain current (a) v ds , drain to source voltage (v) v gs = -1.5v t a = 25 o c pulse duration = 80 s duty cycle = 0.5% max 0 -5 -10 -15 -20 -25 0 -0.5 -1.0 -1.5 -2.0 v gs = -3v v gs = -4.5v v gs = -2.5v v gs = -2v 10 20 30 40 50 -1 -2 -3 -4 -5 i d = -2a v gs , gate to source voltage (v) i d = -9a r ds(on) , drain to source on resistance (m ? ) pulse duration = 80 s duty cycle = 0.5% max 1.0 1.4 1.6 0.6 0.8 1.2 -80 -40 0 40 80 120 160 normalized drain to source t j , junction temperature ( o c) on resistance v gs = -4.5v, i d = -9a pulse duration = 80 s duty cycle = 0.5% max 0.4 0.6 0.8 1.0 1.2 1.4 -80 -40 0 40 80 120 160 normalized gate t j , junction temperature ( o c) v gs = v ds , i d = -250 a threshold voltage ITF87068SQT
5 figure 11. normalized drain to source breakdown voltage vs junction temperature figure 12. capacitance vs drain to source voltage note: refer to intersil application notes an7254 and an7260. figure 13. gate charge waveforms for constant gate current figure 14. switching time vs gate resistance figure 15. switching time vs gate resistance typical performance curves (continued) 0.95 1.0 1.05 1.1 -80 -40 0 40 80 120 160 t j , junction temperature ( o c) normalized drain to source breakdown voltage i d = -250 a 100 1000 -0.1 -1 -10 5000 -20 c, capacitance (pf) v ds , drain to source voltage (v) v gs = 0v, f = 1mhz c iss = c gs + c gd c oss ? c ds + c gd c rss = c gd 0 -1 -2 -3 -4 -5 0 5 10 15 20 25 30 35 v gs , gate to source voltage (v) v dd = -10v q g , gate charge (nc) i d = -9a i d = -2a waveforms in descending order: 0 100 200 300 400 0 1020304050 switching time (ns) r gs , gate to source resistance ( ? ) v gs = -2.5v, v dd = -10v, i d = -4.5a t d(off) t r t f t d(on) 0 100 200 300 400 0 1020304050 switching time (ns) r gs , gate to source resistance ( ? ) v gs = -4.5v, v dd = -10v, i d = -9a t d(off) t r t d(on) t f ITF87068SQT
6 thermal resistance vs mounting pad area the maximum rated junction temperature, t jm , and the thermal resistance of the heat dissipating path determines the maximum allowable device power dissipation, p dm , in an application. therefore the applications ambient temperature, t a ( o c), and thermal resistance r ja ( o c/w) must be reviewed to ensure that t jm is never exceeded. equation 1 mathematically represents the relationship and serves as the basis for establishing the rating of the part. in using surface mount devices such as the tssop-8 package, the environment in which it is applied will have a signi?ant in?ence on the parts current and maximum power dissipation ratings. precise determination of p dm is complex and in?enced by many factors: 1. mounting pad area onto which the device is attached and whether there is copper on one side or both sides of the board. 2. the number of copper layers and the thickness of the board. 3. the use of external heat sinks. 4. the use of thermal vias. 5. air ?w and board orientation. 6. for non steady state applications, the pulse width, the duty cycle and the transient thermal response of the part, the board and the environment they are in. intersil provides thermal information to assist the designers preliminary application evaluation. figure 20 de?es the r ja for the device as a function of the top copper (component side) area. this is for a horizontally positioned fr-4 board with 1oz copper after 1000 seconds of steady state power with no air ?w. this graph provides the test circuits and waveforms figure 16. gate charge test circuit figure 17. gate charge waveforms figure 18. switching time test circuit figure 19. switching time waveform r l v gs + - v ds v dd dut i g(ref) v dd q g(th) v gs = -0.5v q g(-2) v gs = -2v q g(tot) v gs = -4.5v v ds -v gs i g(ref) 0 0 q gs q gd r gs r l dut -v gs 0v + - v gs v ds t d(on) t r 90% 10% v ds 90% t f t d(off) t off 90% 50% 50% 10% pulse width v gs t on 10% 0 0 (eq. 1) p dm t jm t a () z ja ------------------------------ - = ITF87068SQT
7 necessary information for calculation of the steady state junction temperature or power dissipation. pulse applications can be evaluated using the intersil device spice thermal model or manually utilizing the normalized maximum transient thermal impedance curve. displayed on the curve are r ja values listed in the electrical specifications table. the points were chosen to depict the compromise between the copper board area, the thermal resistance and ultimately the power dissipation, p dm . thermal resistances corresponding to other copper areas can be obtained from figure 20 or by calculation using equation 2. r ja is defined as the natural log of the area times a coefficient added to a constant. the area, in square inches is the top copper area including the gate and source pads. the transient thermal impedance (z ja ) is also effected by varied top copper board area. figure 21 shows the effect of copper pad area on single pulse transient thermal impedance. each trace represents a copper pad area in square inches corresponding to the descending list in the graph. spice and saber thermal models are provided for each of the listed pad areas. copper pad area has no perceivable effect on transient thermal impedance for pulse widths less than 100ms. for pulse widths less than 100ms the transient thermal impedance is determined by the die and package. therefore, ctherm1 through ctherm5 and rtherm1 through rtherm5 remain constant for each of the thermal models. a listing of the model component values is available in table 1. (eq. 2) r ja 97.5 20.2 area () ln = figure 20. thermal resistance vs mounting pad area 120 160 180 240 0.1 1.0 80 0.001 r ja = 97.5 - 20.2* ln (area) 165.4 o c/w - 0.035in 2 206.8 o c/w - 0.0045in 2 r ja ( o c/w) area, top copper area (in 2 ) 140 100 0.01 200 220 figure 21. thermal impedance vs mounting pad area 30 60 90 120 150 0 10 -1 10 0 10 1 10 2 10 3 t, rectangular pulse duration (s) z ja , thermal copper board area - descending order 0.04 in 2 0.28 in 2 0.52 in 2 0.76 in 2 1.00 in 2 impedance ( o c/w) ITF87068SQT
8 pspice electrical model .subckt itf87068sq 2 1 3 ; rev 25 jan 2000 ca 12 8 2.8e-9 cb 15 14 2.8e-9 cin 6 8 2.7e-9 dbody 5 7 dbodymod dbreak 7 11 dbreakmod desd1 91 9 desd1mod desd2 91 7 desd2mod dplcap 10 6 dplcapmod ebreak 5 11 17 18 -31.3 eds 14 8 5 8 1 egs 13 8 6 8 1 esg 5 10 8 6 1 evthres 6 21 19 8 1 evtemp 6 20 18 22 1 it 8 17 1 ldrain 2 5 1.0e-9 lgate 1 9 4.4e-9 lsource 3 7 4.5e-9 mmed 16 6 8 8 mmedmod mstro 16 6 8 8 mstromod mweak 16 21 8 8 mweakmod rbreak 17 18 rbreakmod 1 rdrain 50 16 rdrainmod 5.8e-3 rgate 9 20 3.5 rldrain 2 5 10 rlgate 1 9 9 44 rlsource 3 7 45 rslc1 5 51 rslcmod 1e-6 rslc2 5 50 1e3 rsource 8 7 rsourcemod 3.2e-3 rvthres 22 8 rvthresmod 1 rvtemp 18 19 rvtempmod 1 s1a 6 12 13 8 s1amod s1b 13 12 13 8 s1bmod s2a 6 15 14 13 s2amod s2b 13 15 14 13 s2bmod vbat 22 19 dc 1 eslc 51 50 value={(v(5,51)/abs(v(5,51)))*(pwr(v(5,51)/(1e-6*200),2.8))} .model dbodymod d (is = 2.8e-10 rs = 4.7e-3 trs1 = 1.75e-3 trs2 = -1.0e-6 n = 1.08 ikf = 0.8 cjo = 1.2e-9 tt = 1.0e-9 m = 0.5) .model dbreakmod d (rs = 3.5e-1 trs1 = 1.0e-3 trs2 = -2.0e-5) .model desd1mod d (bv=12.2 tbv1= -2.0e-3 rs=35 n=12.4) .model desd2mod d (bv=12.4 tbv1= -2.0e-3 rs=35 n=12.5) .model dplcapmod d (cjo = 1.25e-9 is = 1e-30 n=10 vj=0.39 m = 0.41) .model mmedmod pmos (vto = -1.0 kp = 35 is = 1e-30 n = 10 tox = 1 l = 1u w = 1u rg = 3.5 rs = 0.1) .model mstromod pmos (vto = -1.16 kp = 100 is = 1e-30 n = 10 tox = 1 l = 1u w = 1u) .model mweakmod pmos (vto = -0.7 kp = 0.1 is = 1e-30 n = 10 tox = 1 l = 1u w = 1u rg = 35 rs = 0.1) .model rbreakmod res (tc1 = 6.3e-4 tc2 = -5.0e-7) .model rdrainmod res (tc1 = 5.0e-3 tc2 = 1.2e-6) .model rslcmod res (tc1 = 1.0e-3 tc2 = 1.0e-6) .model rsourcemod res (tc1 = 1e-3 tc2 = 1e-6) .model rvthresmod res (tc1 = 1.2e-3 tc2 = 4.9e-6) .model rvtempmod res (tc1 = -3.3e-4 tc2 = -1.0e-7) .model s1amod vswitch (ron = 1e-5 roff = 0.1 von = 2.5 voff= 1.5) .model s1bmod vswitch (ron = 1e-5 roff = 0.1 von = 1.5 voff= 2.5) .model s2amod vswitch (ron = 1e-5 roff = 0.1 von = 0.75 voff= -0.5) .model s2bmod vswitch (ron = 1e-5 roff = 0.1 von = -0.5 voff= 0.75) .ends note: for further discussion of the pspice model, consult a new pspice sub-circuit for the power mosfet featuring global temperature options ; ieee power electronics specialist conference records, 1991, written by william j. hepp and c. frank wheatley. 18 22 - + + - 5 51 + - 19 8 + - 17 18 6 8 + - 5 8 + - rbreak rvtemp vbat rvthres it 17 18 19 22 12 13 15 s1a s1b s2a s2b ca cb egs eds 14 8 13 8 14 13 mweak dbody rsource source 11 7 3 lsource rlsource cin rdrain evthres 16 21 8 mmed mstro drain 2 ldrain rldrain dbreak dplcap eslc rslc1 10 5 51 50 rslc2 1 gate rgate evtemp 9 esg lgate rlgate 20 + - + - + - 8 6 ebreak desd1 desd2 91 6 ITF87068SQT
9 saber electrical model rev 25 jan 2000 template itf87068sq n2,n1,n3 electrical n2,n1,n3 { var i iscl dp..model dbodymod = (isl = 2.8e-10, nl = 1.08, cjo = 1.2e-9, tt = 1.0e-9, m = 0.5, rs = 4.7e-3, trs1 = 1.75e-3, trs2 = -1.0e- 6, ikf = 0.8) dp..model dbreakmod = (rs = 3.5e-1, trs1 = 1.0e-3, trs2 = -2.0e-5) dp..desd1mod = (bv = 12.2, tbv1 = -2.0e-3, rs = 35, nl = 12.4) dp..desd2mod = (bv = 12.4, tbv1 = -2.0e-3, rs = 35, nl = 12.5) dp..model dplcapmod = (cjo = 1.25e-9, isl = 10e-30, nl = 10, vj=0.39, m = 0.41 ) m..model mmedmod = (type=_p, vto = -1.0, kp = 35, is = 1e-30, tox = 1, rs=0.1) m..model mstrongmod = (type=_p, vto = -1.16, kp = 100, is = 1e-30, tox = 1) m..model mweakmod = (type=_p, vto = -0.7, kp = 0.1, is = 1e-30, tox = 1 rs=0.1) sw_vcsp..model s1amod = (ron = 1e-5, roff = 0.1, von = 2.5, voff = 1.5) sw_vcsp..model s1bmod = (ron =1e-5, roff = 0.1, von = 1.5, voff = 2.5) sw_vcsp..model s2amod = (ron = 1e-5, roff = 0.1, von = 0.75, voff = -0.5) sw_vcsp..model s2bmod = (ron = 1e-5, roff = 0.1, von = -0.5, voff = 0.75) c.ca n12 n8 = 2.8e-9 c.cb n15 n14 = 2.8e-9 c.cin n6 n8 = 2.7e-9 dp.dbody n5 n7 = model=dbodymod dp.dbreak n7 n11 = model=dbreakmod dp.dplcap n10 n6 = model=dplcapmod dp.desd1 n91 n9 = model=desd1mod dp.desd2 n91 n7 = model=desd2mod i.it n8 n17 = 1 l.ldrain n2 n5 = 1.0e-9 l.lgate n1 n9 = 4.4e-9 l.lsource n3 n7 = 4.5e-9 m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u res.rbreak n17 n18 = 1, tc1 = 6.3e-4, tc2 = -5.0e-7 res.rdrain n50 n16 = 5.8e-3, tc1 = 5.0e-3, tc2 = 1.2e-6 res.rgate n9 n20 = 3.5 res.rldrain n2 n5 = 10 res.rlgate n1 n9 = 44 res.rlsource n3 n7 = 45 res.rslc1 n5 n51 = 1e-6, tc1 = 1.0e-3, tc2 = 1.0e-6 res.rslc2 n5 n50 = 1e3 res.rsource n8 n7 = 3.2e-3, tc1 = 1.0e-3, tc2 = 1.0e-6 res.rvtemp n18 n19 = 1, tc1 = -3.3e-4, tc2 = -1.0e-7 res.rvthres n22 n8 = 1, tc1 = 1.2e-3, tc2 = 4.9e-6 spe.ebreak n11 n7 n17 n18 = -31.3 spe.eds n14 n8 n5 n8 = 1 spe.egs n13 n8 n6 n8 = 1 spe.esg n5 n10 n8 n6 = 1 spe.evtemp n6 n20 n18 n22 = 1 spe.evthres n6 n21 n19 n8 = 1 sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod v.vbat n22 n19 = dc=1 equations { i (n51->n50) +=iscl iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/200))** 2.8)) } } 18 22 + - 19 8 + - 17 18 6 8 + - 5 8 + - rbreak rvtemp vbat rvthres it 17 18 19 22 12 13 15 s1a s1b s2a s2b ca cb egs eds 14 8 13 8 14 13 mweak ebreak dbody rsource source 11 7 3 lsource rlsource cin rdrain evthres 16 21 8 mmed mstro drain 2 ldrain rldrain dbreak dplcap iscl rslc1 10 5 51 50 rslc2 1 gate rgate evtemp 9 esg lgate rlgate 20 + - + - + - 6 desd1 desd2 91 8 6 + - ITF87068SQT
10 spice thermal model rev 27 december 1999 ITF87068SQT copper area = 1.0 in 2 ctherm1 th 8 1.5e-3 ctherm2 8 7 5.0e-3 ctherm3 7 6 1.0e-2 ctherm4 6 5 2.0e-2 ctherm5 5 4 5.0e-2 ctherm6 4 3 0.2 ctherm7 3 2 0.5 ctherm8 2 tl 3.0 rtherm1 th 8 0.15 rtherm2 8 7 0.5 rtherm3 7 6 1.25 rtherm4 6 5 8 rtherm5 5 4 12 rtherm6 4 3 12 rtherm7 3 2 18 rtherm8 2 tl 25 saber thermal model copper area = 1.0 in 2 template thermal_model th tl thermal_c th, tl { ctherm.ctherm1 th 8 = 1.5e-3 ctherm.ctherm2 8 7 = 5.0e-3 ctherm.ctherm3 7 6 = 1.0e-2 ctherm.ctherm4 6 5 = 2.0e-2 ctherm.ctherm5 5 4 = 5.0e-2 ctherm.ctherm6 4 3 = 0.2 ctherm.ctherm7 3 2 = 0.5 ctherm.ctherm8 2 tl = 3.0 rtherm.rtherm1 th 8 = 0.15 rtherm.rtherm2 8 7 = 0.5 rtherm.rtherm3 7 6 = 1.25 rtherm.rtherm4 6 5 = 8 rtherm.rtherm5 5 4 = 12 rtherm.rtherm6 4 3 = 12 rtherm.rtherm7 3 2 = 18 rtherm.rtherm8 2 tl = 25 } rtherm6 rtherm8 rtherm7 rtherm5 rtherm4 rtherm3 ctherm4 ctherm6 ctherm5 ctherm3 ctherm2 ctherm1 tl 2 3 4 5 6 7 junction case 8 th rtherm2 rtherm1 ctherm7 ctherm8 table 1. thermal models component 0.04 in 2 0.28 in 2 0.52 in 2 0.76 in 2 1.0 in 2 ctherm6 0.12 0.2 0.28 0.19 0.2 ctherm7 0.25 0.48 0.45 0.39 0.5 ctherm8 1.3 2.3 2.2 2.7 3.0 rtherm6 26 20 15 11 12 rtherm7 39 24 21 21 18 rtherm8 49.5 36.8 39 29.5 25 ITF87068SQT
11 ITF87068SQT mo-153aa (tssop-8) 8 lead jedec mo-153aa tssop plastic package mo-153aa (tssop-8) 12mm tape and reel a a 1 l d e 1 e b e 58 c 0 o -8 o 0.004 in 0.10mm 4 0.015 0.4 0.232 5.9 0.035 0.9 0.025 0.65 0.077 1.95 symbol inches millimeters notes min max min max a 0.041 0.047 1.05 1.20 - a 1 0.002 0.006 0.05 0.15 - b 0.010 0.012 0.25 0.30 - c 0.005 0.127 - d 0.114 0.122 2.90 3.10 2 e 0.244 0.260 6.20 6.60 - e 1 0.170 0.177 4.30 4.50 3 e 0.025 bsc 0.65 bsc - l 0.020 0.028 0.50 0.70 4 notes: 1. these dimensions are within allowable dimensions of rev. e of jedec mo-153aa outline dated 10-97. 2. dimension ? does not include mold flash, protrusions or gate burrs. mold flash, protrusions or gate burrs shall not exceed 0.006 inches (0.15mm) per side. 3. dimension ? 1 does not include inter-lead flash or protrusions. interlead flash and protrusions shall not exceed 0.010 inches (0.25mm) per side. 4. ??is the length of terminal for soldering. 5. controlling dimension: millimeter 6. revision 3 dated: 5-00. user direction of feed general information 1. 3000 pieces per reel. 2. order in multiples of full reels only. 3. meets eia-481 revision "a" specifications. 330mm 100mm 13mm 17.4mm 13.4mm cover tape l c dia. hole 1.5mm 1.75mm 4.0mm 2.0mm 12mm 8.0mm
12 all intersil semiconductor products are manufactured, assembled and tested under iso9000 quality systems certi?ation. intersil semiconductor products are sold by description only. intersil corporation reserves the right to make changes in circuit design and/or spec ifications at any time with- out notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnished by intersil is b elieved to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of th ird parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see web site www.intersil.com sales of?e headquarters north america intersil corporation p. o. box 883, mail stop 53-204 melbourne, fl 32902 tel: (321) 724-7000 fax: (321) 724-7240 europe intersil sa mercure center 100, rue de la fusee 1130 brussels, belgium tel: (32) 2.724.2111 fax: (32) 2.724.22.05 asia intersil ltd. 8f-2, 96, sec. 1, chien-kuo north, taipei, taiwan 104 republic of china tel: 886-2-2515-8508 fax: 886-2-2515-8369 ITF87068SQT

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